Communication products, such as two-way radios, cell phones and the like, utilize a variety of integrated circuits to minimize size, cost and weight. Many of these products, as well as other electronic devices, utilize mixed signal technology wherein both digital and analog functions are processed for multi-mode and multi-band specifications. The efficient operation of a mixed signal device is critical to the overall operation of the end product into which the device is incorporated. A digital-to-analog converter (DAC) is one such circuit that can be integrated either alone or as part of a more complex integrated circuit.
The development, production and testing of mixed signal technology die is time consuming and costly. In addition, final testing of complex integrated circuits incorporating DACs require more test time, which drives up the cost associated with the part. Previous approaches to DAC self-testing have relied on complex test architectures, such as those incorporating an analog-to-digital converter (ADC). While some self-testing capability has been achieved on small DACs (such as a 4 bit or 5 bit DACs), the area required to accomplish this testing becomes prohibitively large as DACs become larger.
Accordingly, there is need for an improved approach for self-testing a DAC in an integrated circuit.
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The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.